Prior to the mid-1970s, MOS technology was utilized primarily for memory and logic functions, and the analog functions such as operational amplifiers were typically implemented by using bipolar integrated circuits [Paul R. Gray et al., Analysis and Design of Analog Integrated Circuits, second edition, John Wiley & Sons]. However, in recent years, the steady increases in chip complexity brought about by continuing improvements in lithographic resolutions have created the economic incentive to implement subsystems or systems containing both analog and digital functions on a single mixed-signal integrated circuit or a single system-on-chip. In addition, the steady increases in memory chip density have demand the economic incentive to implement systems containing both analog and memory functions on a single memory integrated circuit, a multi-die package (i.e., multi-die in a single package), or a same printed circuit board. In single mixed-signal IC (i.e., integrated circuit), single memory IC or single system-on-chip, the problem of digital noise coupling is not negligible and the circuit and methodology for its avoidance are very important. Digital noise coupling has been caused by capacitive couplings, coupling through power supply, and coupling through substrate or ground. Thus, in order to solve one of digital noise coupling problems, it has required extra pins so that separate pins for analog functional section and digital functional section (or memory functional section) are used. It is here assumed that one pad is connected to one pin.
Prior Art FIG. 1 illustrates a circuit diagram of conventional separate pins for an analog functional section and a digital functional section for mixed-signal IC (i.e., integrated circuit) and SOC (i.e., system-on-chip). Prior Art FIG. 1 is comprised of an analog functional section coupled between a positive analog power supply 151 and a negative analog power supply (or analog ground) 161, and also composed of a digital functional section coupled between a positive digital power supply 152 and a negative digital power supply (or digital ground) 162. Unfortunately, the conventional separate pins for an analog functional section and a digital functional section 100 is very expensive to implement in integrated circuit (IC) chip because more number of pins has greatly increased the chip cost as well as printed circuit board cost.
Thus, what is needed is cost-effective pin number reduction circuit for mixed-signal IC, memory IC, and SOC that can be efficiently implemented along with minimizing digital noise coupling and maximizing marketing advantages. The present invention satisfies these needs by providing pin number reduction circuit and methodology for mixed-signal IC, memory IC, and SOC basically utilizing resistors, capacitors, transistors, and amplifiers.